1. Field of the Invention
The present invention relates to a semiconductor integrated circuit such as a Dynamic Random Access Memory (DRAM) or the like, and, in particular, to a semiconductor integrated circuit which is capable of extending operating margin of a bit line equalizer in a low voltage range with high reliability.
2. Description of the Prior Art
Problems involved in conventional semiconductor integrated circuits will now be explained with reference to FIGS. 1, 2, and 3. In the following explanation, where the name of a signal line is followed by the symbol # this signifies that the signal line operates a negative logic signal.
In FIG. 1 a plurality of memory cells, for example cells C1 and C2, are connected to a bit line pair BL0 and BL0#. At the rising edge of a word line WL0 or WL1 selected at a row address, a charge stored in a capacitor in a memory cell is transferred to a bit line which has already equalized by an equalizer El, so that a small potential difference is produced between the bit lines BL0 and BL0#.
A pair of NMOS transistors N1 and N2 as transfer gates transmit the potential difference in the bit lines BL0 and BL0#to nodes L1 and L2, and the small potential difference is sensed by a sense amplifies S1 consists of NMOS transistors N3 and N4 operated by an activated signal SAN#.
At this time, a control signal .phi. T for the transfer gates N1 and N2 is at the power source potential (Vcc) level. Because the pair of bit lines BL0 and BL0# are at an intermediate potential at the sensing or equalizing, the voltage difference between a source and a bulk (a substrate) of each of the transfer gates N1 and N2 is high, therefore the threshold voltage of the transfer gates N1 and N2 becomes a high value, and the bit line capacitors of the bit lines BL0# and BL0 which is a relatively large is not affected by the nodes L1 and L2. This, therefore, effectively raises the sense margin.
Next, when the bit lines BL0# and BL0 enter a precharge cycle, a control signal EQL# for an NMOS transistor N5, which is an equalizing gate for an equalizing circuit El, is at the H level, and then an equalizing operation for the bit lines BL0 and BL0# is started.
FIG. 2A shows a conventional equalizing circuit E2 having another configuration to which have been added NMOS transistors N7 and N8, which supply a signal VBL of 1/2 Vcc level to the equalizing circuit El, as shown in FIG. 1. The bit lines BL0 and BL0# can be precharged to 1/2 Vcc level by the equalizing circuit E2.
FIG. 2B is a conventional circuit diagram for a sense amplifier S2 used for a restore operation which write data on the bit lines BL0 and BL0# to the memory cells C1 and C2. The sense amplifier S2 consists of a pair of PMOS transistors P1 and P2. Because the sense amplifier S1 shown in FIG. 1 is a circuit for amplifying a bit line of a lower potential in the bit lines BL0 and BL0# at the falling edge of an activation signal SAN#, the sense amplifier S2 used for the restore operation, shown separately in FIG. 2B, is necessary for setting the bit line on the side which is at the H level to the Vcc level.
In the sense amplifier S2 for the restore operation, the bit line of the H level is amplified at the rising edge in an activation signal SAP. When the activation signal SAN# falls down and there is some voltage difference between the nodes L1 and L2, the activation signal is raised.
The above circuit configuration of the pair of the equalizing circuit E2 and the sense amplifier S2 is one part of a column in the DRAM, and a plurality of the circuits of this type exists on a memory chip of a DRAM.
There is a problem on the read/write operation in this type of DRAM of the conventional semiconductor integrated circuit in which the equalization for the bit lines BL0 and BL0# cannot be completed when the DRAM operates with a lower source voltage.
An explanation of the conventional problem described above will now be made with reference to the timing chart shown in FIG. 3, which represents the state of the signal lines and nodes.
At the previous active cycle, a word line WLO is selected, and data stored in the memory cell C2 is transmitted to the bit line BL0 and the node L2 which are at a Low level (L level). When a row address strobe signal RAS# is changed from the L level to a High level (H level) and the bit line BL0 and BL0# enter a precharge cycle, the word line WLO enters a V.sub.SS level, the activation signals SAN# and SAP a V.sub.BL level, the control signal .phi. T the V.sub.CC level, and the control signal line EQL# the V.sub.CC level. Then, a VBL precharge operation and the equalizing operation are commenced for the bit lines BL0 and BL0#.
Specifically, the V.sub.BL level supply from the NMOS transistor N8 in the equalizing circuit E2 to the bit line BL0 of the L leveled is commenced. The V.sub.BL level supply from the NMOS transistor N7 in the equalizing circuit E2 is commenced to the bit line BL0# of the H level. In this case, the voltage potential of the bit line BL0# is decreased. In addition, an equalizing operation, whereby the bit lines BL0 and BL0# at H and L levels are shorted, is commenced by the NMOS transistor N6.
When the relationship among the voltage potentials of the various transistors are observed at this time, the V.sub.BL level is applied to the drain, the V.sub.CC level to the gate, and a V.sub.BB level to the bulk or the substrate, in the NMOS transistor N8. The bit line BL0 of the L level, which is connected to the source, is charged from the V.sub.SS level to the V.sub.BL level.
The V.sub.BL level is applied to the source and the V.sub.CC level to the gate in the NMOS transistor N7. The bulk voltage becomes the (V.sub.BL -V.sub.BB) level and is higher than that of the NMOS transistor N8. For this reason, the threshold value of the NMOS transistor N7 becomes extremely high by the bulk bias reliability of the transistors, and the transconductance gm of the NMOS transistor N7 drops to approximately a OFF state.
In addition, the transistor characteristic such as the transconductance of the NMOS transistor N6 in the equalizing circuit E2, in which the bit line BL0 of the L level is connected to the source of the NMOS transistor N6 and the bit line BL0# of the H level to the drain of the NMOS transistor N6, becomes approximately equal to the transistor characteristics of the NMOS transistor N7 in accordance with the increasing of the bit line BL0 of the L level (the voltage potential of the bit line BL0) under the condition that the gate of the NMOS transistor N6 is in the V.sub.CC level and the bulk of the NMOS transistor N6 is in the V.sub.BB level.
There is no circuit performing the precharge and equalizing operations in the nodes L1 and L2, but these nodes are supplied from the bit lines BL0 and BL0#. Therefore the H level of the node L1 is a voltage which is less than the threshold value of the NMOS transistor N1. The source of the NMOS transistor N1 is connected to the node L1, therefore the NMOS transistor N1 is nearly in the OFF state. The reason that the node L1 is in the V.sub.BL level is that the precharge operation of the node L1 is started after the potential voltage of the bit line BL0# is less than that of the node L1, so that the efficiency is very poor.
Next, the case in which the active cycle is entered from this state described above will be considered.
The row address strobe signal RAS# is changed from the H level to the L level, the row address is selected so that the control signal EQL# for the equalizing circuit E2 is at the L level, the voltage potential of the selected word line WL1 rises and the data stored in the memory cell C1 is transmitted to the bit lines BL0 and BL0#.
At this time the memory cell C1 stores the data of zero level "0". However, in this case, until the control signal EQL# falls, the equalizing of the bit lines BL0 and BL0# and the nodes L1 and L2 cannot be completed adequately, therefore even when the data of zero level "0" is read out on the bit line BL0#, the bit line BL0 becomes as the bit line of the H level becomes lower than that of the bit line BL0#, therefore the data of the high level "1" is erroneously read out as the state of the low level "0".
As outlined above, when a lower source voltage is used for executing a conventional semiconductor integrated circuit such as a DRAM, there is the problem that the equalizing operation for bit lines cannot be completed within the precharge operation period so that an erroneous operation occurs.